The present invention relates to a method for fabricating semiconductor devices. More particularly, the present invention relates to a semiconductor device with a recess gate therein and a method for fabricating the same.
Generally, semiconductor memory devices are fabricated through a fabrication (FAB) process, for repeatedly forming circuit patterns set on a substrate to form cells with integrated circuits, and an assembly process, for packaging the substrate with the cells on a chip basis. Furthermore, an electrical die sorting (EDS) process for checking an electric characteristic of the cells over the substrate is performed between the above two processes.
Defective cells are sorted out through the EDS process. Prepared redundancy cells substitute for the sorted defective cells by a repair process. Thus, the chips normally operate and the throughput of the semiconductor memory device increases.
The repair process is performed by a fuse blowing method irradiating a laser beam onto a line connected to the defective cells to cut the line. The line cut by the laser beam is called a fuse. A portion surrounding the cut fuse is called a fuse portion. The fuse unit includes a fuse, an insulation layer over the fuse, and a fuse box formed by etching a portion of the insulation layer. The laser beam can be irradiated to the fuse box to cut the fuse. To successfully cut the fuse with the laser beam, it is required to properly adjust a thickness (Rox) of the insulation layer remaining over the fuse in the fuse box. That is, when the insulation layer remaining over the fuse is overly thick, explosive power of the fuse becomes increases. Thus, an adjacent fuse may be attacked or the substrate below the fuse may be cracked. When the insulation layer remaining over the fuse is overly thin, the fuse is not cut.
A typical fuse is formed using a polysilicon plate electrode of a capacitor in a cell region. However, as semiconductor devices are highly integrated and an electric characteristic of the semiconductor devices is secured, a three-layered metal line is formed instead of a typical two-layered metal line during a metal line formation process. Furthermore, an etch target increases during a formation of the fuse unit including the fuse formed using the polysilicon plate electrode. In the formation of the fuse unit, etch time and height difference increases. Thus, it is difficult to control the thickness (Rox) of the insulation layer remaining on the fuse.
Currently, a fuse is formed using a metal line. Hereinafter, the fuse formed using the metal line is called as a metal fuse. The metal fuse is disposed higher than the fuse formed using the polysilicon plate electrode. Thus, an etch target decreases when the insulation layer for forming a fuse box is etched.
However, since the metal fuse has a lower resistance than the polysilicon fuse, the thickness (Rox) of the metal fuse remaining on the metal fuse is less than that remaining on the fuse. That is, a range of the thickness (Rox) of the insulation layer remaining on the metal fuse is smaller than that remaining on using the polysilicon fuse. Thus, it is difficult to control the extent of etch during the formation of the fuse box and fabricate the semiconductor devices in mass.
Furthermore, the metal line and the metal fuse formed using the metal line does not include one material like the polysilicon fuse. That is, the metal line and the metal fuse formed using the metal line may have a stack structure of TiN/Al/TiN. Thus, defect occurrence possibility increases when the fuse using the laser beam is cut out. This is because the barrier metal layer below the metal fuse often protrudes during a metal etch process and insufficient energy is supplied to this protruded portion during a subsequent fuse blowing process, which thus remains as a residue.